PHIDEO: high-level synthesis for high throughput applications
Journal of VLSI Signal Processing Systems - Special issue on design environments for DSP
Allocation of multiport memories for hierarchical data stream
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
YAPI: application modeling for signal processing systems
Proceedings of the 37th Annual Design Automation Conference
Stream communication between real-time tasks in a high-performance multiprocessor
Proceedings of the conference on Design, automation and test in Europe
MPEG Video Compression Standard
MPEG Video Compression Standard
Multidimensional Periodic Scheduling Model and Complexity
Euro-Par '96 Proceedings of the Second International Euro-Par Conference on Parallel Processing-Volume II
A scalable and flexible data synchronization scheme for embedded HW-SW shared-memory systems
Proceedings of the 14th international symposium on Systems synthesis
The Cost of Communication Protocols and Coordination Languages in Embedded Systems
COORDINATION '02 Proceedings of the 5th International Conference on Coordination Models and Languages
Embedded Systems Design
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In high-throughput real-time media processing systems, the communication between processing units is typically specified as multi-dimensional arrays. However, the implementation of such applications is mostly FIFO-based. Mapping array communication onto a FIFO-based implementation requires complex address generators if the arrays have multiple dimensions. In this paper, we present a method for mapping array communication onto an efficient microcomputer architecture implementation based on FIFO communication via shared memory. A good hardware/software partitioning for the address generation is proposed. Furthermore, a complete design flow from specification to implementation is described. We illustrate this method with a design case: the communication of video frames between the frontend and the compressor in an MPEG encoder.