Thread-parallel MPEG-2, MPEG-4 and H.264 video encoders for SoC multi-processor architectures

Authors:
T. R. Jacobs;V. A. Chouliaras;D. J. Mulvaney
Affiliations:
Loughborough Univ., UK;-;-
Venue:
IEEE Transactions on Consumer Electronics
Year:
2006

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Abstract

This study utilizes thread-level parallel techniques to significantly reduce the dynamic instruction count performance metric of the MPEG-2, MPEG-4 and H.264 video encoders. Such solutions are particularly applicable in portable devices as workload distribution among a number of parallel-executing processors decreases the individual processing requirements and allows for the real time video encoding. Due to the use of multiple processing engines in a consumer SoC the required clock frequency for real-time encoding, and hence power consumption, is likely to be considerably less than that of a single high-speed processor solution. The results presented demonstrate that reductions in dynamic instruction count in the range of 84% to 96% can be achieved for each of the encoders investigated.