Transactional memory: architectural support for lock-free data structures
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Software and the Concurrency Revolution
Queue - Multiprocessors
The next mainstream programming language: a game developer's perspective
Conference record of the 33rd ACM SIGPLAN-SIGACT symposium on Principles of programming languages
McRT-STM: a high performance software transactional memory system for a multi-core runtime
Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming
Compiler and runtime support for efficient software transactional memory
Proceedings of the 2006 ACM SIGPLAN conference on Programming language design and implementation
Architectural Semantics for Practical Transactional Memory
Proceedings of the 33rd annual international symposium on Computer Architecture
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Tradeoffs in transactional memory virtualization
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Architectural Support for Software Transactional Memory
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
An effective hybrid transactional memory system with strong isolation guarantees
Proceedings of the 34th annual international symposium on Computer architecture
Programming languages as part of core computer science
ACM SIGPLAN Notices
On Replication of Software Transactional Memories
OPODIS '08 Proceedings of the 12th International Conference on Principles of Distributed Systems
Aspect-oriented support for synchronization in parallel computing
Proceedings of the 1st workshop on Linking aspect technology and evolution
Towards distributed software transactional memory systems
LADIS '08 Proceedings of the 2nd Workshop on Large-Scale Distributed Systems and Middleware
Multi-core parallelization in Clojure: a case study
Proceedings of the 6th European Lisp Workshop
81.6 GOPS object recognition processor based on a memory-centric NoC
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scheduling support for transactional memory contention management
Proceedings of the 15th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming
TMBean: Optimistic Concurrency in Application Servers Using Transactional Memory
OTM '09 Proceedings of the Confederated International Conferences, CoopIS, DOA, IS, and ODBASE 2009 on On the Move to Meaningful Internet Systems: Part I
A breadth-first course in multicore and manycore programming
Proceedings of the 41st ACM technical symposium on Computer science education
Cloud-TM: harnessing the cloud with distributed transactional memories
ACM SIGOPS Operating Systems Review
Generic replication of software transactional memory
Proceedings of the 7th Middleware Doctoral Symposium
A multi-core numerical framework for characterizing flow in oil reservoirs
Proceedings of the 19th High Performance Computing Symposia
TMNOC: a case of HTM and NoC co-design for increased energy efficiency and concurrency
Proceedings of the 21st international conference on Parallel architectures and compilation techniques
| Hi-index | 0.00 |
Multicore architectures are an inflection point in mainstream software development because they force developers to write parallel programs. In a previous article in Queue, Herb Sutter and James Larus pointed out, “The concurrency revolution is primarily a software revolution. The difficult problem is not building multicore hardware, but programming it in a way that lets mainstream applications benefit from the continued exponential growth in CPU performance.” 1 In this new multicore world, developers must write explicitly parallel applications that can take advantage of the increasing number of cores that each successive multicore generation will provide.