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The SPLASH-2 programs: characterization and methodological considerations
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Transactional Memory Coherence and Consistency
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Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming
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Compiler and runtime support for efficient software transactional memory
Proceedings of the 2006 ACM SIGPLAN conference on Programming language design and implementation
Architectural Semantics for Practical Transactional Memory
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Bulk Disambiguation of Speculative Threads in Multiprocessors
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Unbounded page-based transactional memory
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
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Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Queue - Computer Architecture
Architectural Support for Software Transactional Memory
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Subtleties of Transactional Memory Atomicity Semantics
IEEE Computer Architecture Letters
Understanding Tradeoffs in Software Transactional Memory
Proceedings of the International Symposium on Code Generation and Optimization
LogTM-SE: Decoupling Hardware Transactional Memory from Caches
HPCA '07 Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture
A Scalable, Non-blocking Approach to Transactional Memory
HPCA '07 Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture
DISC'06 Proceedings of the 20th international conference on Distributed Computing
Transactions with isolation and cooperation
Proceedings of the 22nd annual ACM SIGPLAN conference on Object-oriented programming systems and applications
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Transactional boosting: a methodology for highly-concurrent transactional objects
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Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming
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SoftSig: software-exposed hardware signatures for code analysis and optimization
Proceedings of the 13th international conference on Architectural support for programming languages and operating systems
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Communications of the ACM - Web science
Proceedings of the 5th conference on Computing frontiers
Inferring locks for atomic sections
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Automatic data partitioning in software transactional memories
Proceedings of the twentieth annual symposium on Parallelism in algorithms and architectures
Checkpoints and continuations instead of nested transactions
Proceedings of the twentieth annual symposium on Parallelism in algorithms and architectures
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RingSTM: scalable transactions with a single atomic instruction
Proceedings of the twentieth annual symposium on Parallelism in algorithms and architectures
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
TokenTM: Efficient Execution of Large Transactions with Hardware Transactional Memory
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Flexible Decoupled Transactional Memory Support
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Rerun: Exploiting Episodes for Lightweight Memory Race Recording
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Software transactional memory: why is it only a research toy?
Communications of the ACM - Remembering Jim Gray
Lee-TM: A Non-trivial Benchmark Suite for Transactional Memory
ICA3PP '08 Proceedings of the 8th international conference on Algorithms and Architectures for Parallel Processing
Maintaining Consistent Transactional States without a Global Clock
SIROCCO '08 Proceedings of the 15th international colloquium on Structural Information and Communication Complexity
Advanced Concurrency Control for Transactional Memory Using Transaction Commit Rate
Euro-Par '08 Proceedings of the 14th international Euro-Par conference on Parallel Processing
Design and implementation of transactional constructs for C/C++
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Software Transactional Memory: Why Is It Only a Research Toy?
Queue - The Concurrency Problem
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An efficient transactional memory algorithm for computing minimum spanning forest of sparse graphs
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Steal-on-Abort: Improving Transactional Memory Performance through Dynamic Transaction Reordering
HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
Recovery domains: an organizing principle for recoverable operating systems
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Maximum benefit from a minimal HTM
Proceedings of the 14th international conference on Architectural support for programming languages and operating systems
WormBench: a configurable workload for evaluating transactional memory systems
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Synthesis from multi-cycle atomic actions as a solution to the timing closure problem
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Notary: Hardware techniques to enhance signatures
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Dependence-aware transactional memory for increased concurrency
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Adaptive Read Validation in Time-Based Software Transactional Memory
Euro-Par 2008 Workshops - Parallel Processing
Fast memory snapshot for concurrent programmingwithout synchronization
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SigRace: signature-based data race detection
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ECMon: exposing cache events for monitoring
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Towards transactional memory semantics for C++
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NZTM: nonblocking zero-indirection transactional memory
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The Bulk Multicore architecture for improved programmability
Communications of the ACM - Finding the Fun in Computer Science Education
SPMTM: A Novel ScratchPad Memory Based Hybrid Nested Transactional Memory Framework
APPT '09 Proceedings of the 8th International Symposium on Advanced Parallel Processing Technologies
Proceedings of the ACM SIGOPS 22nd symposium on Operating systems principles
EazyHTM: eager-lazy hardware transactional memory
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Proactive transaction scheduling for contention management
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Evaluation of AMD's advanced synchronization facility within a complete transactional memory stack
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Directory-based conflict detection in hardware transactional memory
HiPC'08 Proceedings of the 15th international conference on High performance computing
Making nested parallel transactions practical using lightweight hardware support
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Adaptive locks: Combining transactions and locks for efficient concurrency
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LV*: a class of lazy versioning HTMs for low-cost integration of transactional memory systems
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Scalable object-aware hardware transactional memory
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Ad hoc synchronization considered harmful
OSDI'10 Proceedings of the 9th USENIX conference on Operating systems design and implementation
ScalableBulk: Scalable Cache Coherence for Atomic Blocks in a Lazy Environment
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
ASF: AMD64 Extension for Lock-Free Data Structures and Transactional Memory
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InstantCheck: Checking the Determinism of Parallel Programs Using On-the-Fly Incremental Hashing
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Hardware acceleration of transactional memory on commodity systems
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Robust adaptation to available parallelism in transactional memory applications
Transactions on high-performance embedded architectures and compilers III
Efficient partial roll-backing mechanism for transactional memory systems
Transactions on high-performance embedded architectures and compilers III
Understanding bloom filter intersection for lazy address-set disambiguation
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Multiset signatures for transactional memory
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Unified locality-sensitive signatures for transactional memory
Euro-Par'11 Proceedings of the 17th international conference on Parallel processing - Volume Part I
A Well-Balanced Time Warp System on Multi-Core Environments
PADS '11 Proceedings of the 2011 IEEE Workshop on Principles of Advanced and Distributed Simulation
AGC: adaptive global clock in software transactional memory
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Speculative optimizations for parallel programs on multicores
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Hardware transactional memory for GPU architectures
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Transaction reordering to reduce aborts in software transactional memory
Transactions on High-Performance Embedded Architectures and Compilers IV
Improving performance by reducing aborts in hardware transactional memory
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SnCTM: reducing false transaction aborts by adaptively changing the source of conflict detection
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STM systems: enforcing strong isolation between transactions and non-transactional code
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DeAliaser: alias speculation using atomic region support
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The Journal of Supercomputing
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VGTS: variable granularity transactional snoop
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ACM Transactions on Architecture and Code Optimization (TACO)
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We propose signature-accelerated transactional memory (SigTM), ahybrid TM system that reduces the overhead of software transactions. SigTM uses hardware signatures to track the read-set and write-set forpending transactions and perform conflict detection between concurrent threads. All other transactional functionality, including dataversioning, is implemented in software. Unlike previously proposed hybrid TM systems, SigTM requires no modifications to the hardware caches, which reduces hardware cost and simplifies support for nested transactions and multithreaded processor cores. SigTM is also the first hybrid TM system to provide strong isolation guarantees between transactional blocks and non-transactional accesses without additional read and write barriers in non-transactional code. Using a set of parallel programs that make frequent use of coarse-grain transactions, we show that SigTM accelerates software transactions by 30% to 280%. For certain workloads, SigTM can match the performance of a full-featured hardware TM system, while for workloads with large read-sets it can be up to two times slower. Overall, we show that SigTM combines the performance characteristics and strong isolation guarantees of hardware TM implementations with the low cost and flexibility of software TM systems.