Transactional memory: architectural support for lock-free data structures
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
ARB: A Hardware Mechanism for Dynamic Reordering of Memory References
IEEE Transactions on Computers
ICS '98 Proceedings of the 12th international conference on Supercomputing
Data speculation support for a chip multiprocessor
Proceedings of the eighth international conference on Architectural support for programming languages and operating systems
Clustered speculative multithreaded processors
ICS '99 Proceedings of the 13th international conference on Supercomputing
The Superthreaded Processor Architecture
IEEE Transactions on Computers
A scalable approach to thread-level speculation
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Space/time trade-offs in hash coding with allowable errors
Communications of the ACM
Architectural support for scalable speculative parallelization in shared-memory multiprocessors
Proceedings of the 27th annual international symposium on Computer architecture
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HPCA '98 Proceedings of the 4th International Symposium on High-Performance Computer Architecture
HPCA '98 Proceedings of the 4th International Symposium on High-Performance Computer Architecture
Transactional Memory Coherence and Consistency
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Unbounded Transactional Memory
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Evaluating kilo-instruction multiprocessors
WMPI '04 Proceedings of the 3rd workshop on Memory performance issues: in conjunction with the 31st international symposium on computer architecture
Virtualizing Transactional Memory
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An effective hybrid transactional memory system with strong isolation guarantees
Proceedings of the 34th annual international symposium on Computer architecture
Performance pathologies in hardware transactional memory
Proceedings of the 34th annual international symposium on Computer architecture
BulkSC: bulk enforcement of sequential consistency
Proceedings of the 34th annual international symposium on Computer architecture
SoftSig: software-exposed hardware signatures for code analysis and optimization
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TokenTM: Efficient Execution of Large Transactions with Hardware Transactional Memory
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Flexible Decoupled Transactional Memory Support
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Rerun: Exploiting Episodes for Lightweight Memory Race Recording
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Atom-Aid: Detecting and Surviving Atomicity Violations
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Software transactional memory: why is it only a research toy?
Communications of the ACM - Remembering Jim Gray
Scalable and reliable communication for hardware transactional memory
Proceedings of the 17th international conference on Parallel architectures and compilation techniques
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Proceedings of the 14th international conference on Architectural support for programming languages and operating systems
Synthesis from multi-cycle atomic actions as a solution to the timing closure problem
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Notary: Hardware techniques to enhance signatures
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Dependence-aware transactional memory for increased concurrency
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
An analytic framework for performance modeling of software transactional memory
Computer Networks: The International Journal of Computer and Telecommunications Networking
Modeling software transactional memory with AnyLogic
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Fast memory snapshot for concurrent programmingwithout synchronization
Proceedings of the 23rd international conference on Supercomputing
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Proceedings of the 23rd international conference on Supercomputing
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InvisiFence: performance-transparent memory ordering in conventional multiprocessors
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Proceedings of the 36th annual international symposium on Computer architecture
A lightweight in-place implementation for software thread-level speculation
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The Bulk Multicore architecture for improved programmability
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Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
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Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the 37th annual international symposium on Computer architecture
A profile-based tool for finding pipeline parallelism in sequential programs
Parallel Computing
Hardware transactional memory: A high performance parallel programming model
Journal of Systems Architecture: the EUROMICRO Journal
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Journal of Parallel and Distributed Computing
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Implementation tradeoffs in the design of flexible transactional memory support
Journal of Parallel and Distributed Computing
The Paralax infrastructure: automatic parallelization with a helping hand
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A Dynamically Adaptable Hardware Transactional Memory
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The ZCache: Decoupling Ways and Associativity
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Runtime parallelization of legacy code on a transactional memory system
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Multiset signatures for transactional memory
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ZEBRA: a data-centric, hybrid-policy hardware transactional memory design
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Proceedings of the 38th annual international symposium on Computer architecture
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SoC-TM: integrated HW/SW support for transactional memory programming on embedded MPSoCs
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Compiler support for concurrency synchronization
ICA3PP'11 Proceedings of the 11th international conference on Algorithms and architectures for parallel processing - Volume Part I
Global-aware and multi-order context-based prefetching for high-performance processors
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FlexSig: Implementing flexible hardware signatures
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Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Hardware transactional memory for GPU architectures
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Energy and throughput efficient transactional memory for embedded multicore systems
HiPEAC'10 Proceedings of the 5th international conference on High Performance Embedded Architectures and Compilers
SnCTM: reducing false transaction aborts by adaptively changing the source of conflict detection
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Efficient and accurate data dependence profiling using software signatures
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Hardware support for enforcing isolation in lock-based parallel programs
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BlockChop: dynamic squash elimination for hybrid processor architecture
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Monitoring data structures using hardware transactional memory
RV'11 Proceedings of the Second international conference on Runtime verification
An integrated pseudo-associativity and relaxed-order approach to hardware transactional memory
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Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
Energy efficient GPU transactional memory via space-time optimizations
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
Efficient execution of speculative threads and transactions with hardware transactional memory
Future Generation Computer Systems
Removal of Conflicts in Hardware Transactional Memory Systems
International Journal of Parallel Programming
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Transactional Memory (TM), Thread-Level Speculation (TLS), and Checkpointed multiprocessors are three popular architectural techniques based on the execution of multiple, cooperating speculative threads. In these environments, correctly maintaining data dependences across threads requires mechanisms for disambiguating addresses across threads, invalidating stale cache state, and making committed state visible. These mechanisms are both conceptually involved and hard to implement. In this paper, we present Bulk, a novel approach to simplify these mechanisms. The idea is to hash-encode a thread's access information in a concise signature, and then support in hardware signature operations that efficiently process sets of addresses. Such operations implement the mechanisms described. Bulk operations are inexact but correct, and provide substantial conceptual and implementation simplicity. We evaluate Bulk in the context of TLS using SPECint2000 codes and TM using multithreaded Java workloads. Despite its simplicity, Bulk has competitive performance with more complex schemes. We also find that signature configuration is a key design parameter.