The Superthreaded Processor Architecture

  • Authors:

  • Jenn-Yaun Tsai;Jian Huang;Christoffer Amlo;David J. Lilja;Pen-Chung Yew

  • Affiliations:

  • Hewlett-Packard Co., Cupertino, CA;Univ. of Minnesota, Minneapolis;Univ. of Minnesota, Minneapolis;Univ. of Minnesota, Minneapolis;Univ. of Minnesota, Minneapolis

  • Venue:
  • IEEE Transactions on Computers
  • Year:
  • 1999

Quantified Score

Hi-index 14.98

Visualization

Abstract

The common single-threaded execution model limits processors to exploiting only the relatively small amount of instruction-level parallelism available in application programs. The superthreaded processor, on the other hand, is a concurrent multithreaded architecture (CMA) that can exploit the multiple granularities of parallelism available in general-purpose application programs. Unlike other CMAs that rely primarily on hardware for run-time dependence detection and speculation, the superthreaded processor combines compiler-directed thread-level speculation of control and data dependences with run-time data dependence verification hardware. This hybrid of a superscalar processor and a multiprocessor-on-a-chip can utilize many of the existing compiler techniques used in traditional parallelizing compilers developed for multiprocessors. Additional unique compiler techniques, such as the conversion of data speculation into control speculation, are also introduced to generate the superthreaded code and to enhance the parallelism between threads. A detailed execution-driven simulator is used to evaluate the performance potential of this new architecture. It is found that a superthreaded processor can achieve good performance on complex application programs through this close coupling of compile-time and run-time information.