Can dataflow subsume von Neumann computing?
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
T: a multithreaded massively parallel architecture
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
IEEE Transactions on Parallel and Distributed Systems
The Superthreaded Processor Architecture
IEEE Transactions on Computers
A high performance bus and cache controller for PowerPC multiprocessing systems
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
A Novel Approach to Reduce L2 Miss Latency in Shared-Memory Multiprocessors
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Hardware support for real-time embedded multiprocessor system-on-a-chip memory management
Proceedings of the tenth international symposium on Hardware/software codesign
A Simulation Tool for Evaluating Shared Memory Systems
ANSS '03 Proceedings of the 36th annual symposium on Simulation
Analysis of Sharing Overhead in Shared Memory Multiprocessors
HICSS '98 Proceedings of the Thirty-First Annual Hawaii International Conference on System Sciences-Volume 7 - Volume 7
A Cache Coherency Protocol for Optically Connected Parallel Computer Systems
HPCA '96 Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture
The impact of shared-cache clustering in small-scale shared-memory multiprocessors
HPCA '96 Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture
Implementation and Comparison of Distributed Caching Schemes
ICON '00 Proceedings of the 8th IEEE International Conference on Networks
Performance of Shared Cache on Multithreaded Architectures
PDP '96 Proceedings of the 4th Euromicro Workshop on Parallel and Distributed Processing (PDP '96)
Impact of Reducing Miss Write Latencies in Multiprocessors with Two Level Cache
EUROMICRO '98 Proceedings of the 24th Conference on EUROMICRO - Volume 1
Cache Coherence in Intelligent Memory Systems
IEEE Transactions on Computers
| Hi-index | 0.00 |
Many schemes had been used to reduce the performance (or speed) gap between processors and main memories; such as the cache memory is one of the most methods. In this paper, we issue the structure of shared cache, which is based on the multiprocessor architectures to reduce the memory latency time that is the one of major performance bottlenecks of modern processors. In this paper, we mix two schemes, sharing cache and multithreading, to implement this proposed multithreaded architecture with shared cache, to reduce the memory latency and, furthermore improve the processor performance. In this proposed multithreaded architecture, the shared cache is achieved in level-1 (L1) data cache. The L1 shared data cache is combination of cache clock in the single space address and a cache controller to solve the required data transmitting, data copies simultaneously, and reduce memory latency time.