Cache management for discrete processor architectures
ISPA'05 Proceedings of the Third international conference on Parallel and Distributed Processing and Applications
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The PowerPC 620 microprocessor introduces a new integrated secondary cache controller and system bus interface. The secondary cache interface is 128 bits wide, supports L2 sizes from 1 MB to 128 MB, is ECC protected, can transfer 2.0 GB/sec at 133 MHz and supports an optional co-processor mode. The 620 bus is optimized for server-class systems requiring significant multiprocessing capability and supports the 64-bit PowerPC architecture with a 40-bit physical address bus and a separate 128-bit data bus. Address transfer rates of up to 33 M Addresses/sec at 66 MHz are achieved by pipelining the address snoop response with the address bus. The address and data buses are explicitly tagged allowing data transfers to be reordered with respect to the addresses. The data bus can transfer up to 1.0 GB/sec at 66 MHz. The bus protocol and the integrated L2 controller presented support the snoop-based MESI cache coherency protocol and direct cache-to-cache data transfers.