&mgr;C/OS: the real-time kernel
&mgr;C/OS: the real-time kernel
Memory data organization for improved cache performance in embedded processor applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEEE Spectrum
A dynamic memory management unit for embedded real-time system-on-a-chip
CASES '00 Proceedings of the 2000 international conference on Compilers, architecture, and synthesis for embedded systems
A High-Performance Memory Allocator for Object-Oriented Systems
IEEE Transactions on Computers
Dynamic Storage Allocation: A Survey and Critical Review
IWMM '95 Proceedings of the International Workshop on Memory Management
A Hardware Implementation of Realloc Function
WVLSI '99 Proceedings of the IEEE Computer Society Workshop on VLSI'99
Memory traffic and data cache behavior of an MPEG-2 software decoder
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
A High-Performance Hardware-Efficient Memory Allocation Technique and Design
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
A Comparison of Five Different Multiprocessor SoC Bus Architectures
DSD '01 Proceedings of the Euromicro Symposium on Digital Systems Design
Memory management for embedded network applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hardware/software co-synthesis with memory hierarchies
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Hardware-Software Real-Time Operating System Framework for SoCs
IEEE Design & Test
Hardware/Software Partitioning of Operating Systems
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A novel O(n) parallel banker's algorithm for System-on-a-Chip
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A Novel {O(n)} Parallel Banker's Algorithm for System-on-a-Chip
IEEE Transactions on Parallel and Distributed Systems
Exploration of distributed shared memory architectures for NoC-based multiprocessors
Journal of Systems Architecture: the EUROMICRO Journal
The interval page table: virtual memory support in real-time and memory-constrained embedded systems
Proceedings of the 20th annual conference on Integrated circuits and systems design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The accelerator store: A shared memory framework for accelerator-based systems
ACM Transactions on Architecture and Code Optimization (TACO) - HIPEAC Papers
Bandwidth optimization of the EMCI for a high performance 32-bit DSP
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
Cache management for discrete processor architectures
ISPA'05 Proceedings of the Third international conference on Parallel and Distributed Processing and Applications
Power-aware dynamic memory management on many-core platforms utilizing DVFS
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on ESTIMedia'10
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The aggressive evolution of the semiconductor industry --- smaller process geometries, higher densities, and greater chip complexity --- has provided design engineers the means to create complex high-performance Systems-on-a-Chip (SoC) designs. Such SoC designs typically have more than one processor and huge memory, all on the same chip. Dealing with the global on- chip memory allocation/de-allocation in a dynamic yet deterministic way is an important issue for the upcoming billion transistor multiprocessor SoC designs. To achieve this, we propose a memory management hierarchy we call Two-Level Memory Management. To implement this memory management scheme --- which presents a paradigm shift in the way designers look at on-chip dynamic memory allocation --- we present a System-on-a-Chip Dynamic Memory Management Unit (SoCDMMU) for allocation of the global on-chip memory, which we refer to as Level Two memory management (Level One is the operating system management of memory allocated to a particular on-chip Processing Element). In this way, processing elements (heterogeneous or non-heterogeneous hardware or software) in an SoC can request and be granted portions of the global memory in a fast and deterministic time (for an example of a four processing element SoC, the dynamic memory allocation of the global on-chip memory takes sixteen cycles per allocation/deallocation in the worst case). In this paper, we show how to modify an existing Real-Time Operating System (RTOS) to support the new proposed SoCDMMU. Our example shows a multiprocessor SoC that utilizes the SoCDMMU has 440% overall speedup of the application transition time over fully shared memory that does not utilize the SoCDMMU.