Wireless protocols design: challenges and opportunities
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Resolution of dynamic memory allocation and pointers for the behavioral synthesis form C
DATE '00 Proceedings of the conference on Design, automation and test in Europe
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Data and memory optimization techniques for embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Cache-efficient memory layout of aggregate data structures
Proceedings of the 14th international symposium on Systems synthesis
Synthesis of hardware models in C with pointers and complex data structures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Proceedings of the 39th annual Design Automation Conference
A flexible accelerator for layer 7 networking applications
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 2002 international symposium on Low power electronics and design
System-level exploration of association table implementations in telecom network applications
ACM Transactions on Embedded Computing Systems (TECS)
WOSP '02 Proceedings of the 3rd international workshop on Software and performance
Multi-objective abstract data type refinement for mapping tables in telecom network applications
Proceedings of the 2002 workshop on Memory system performance
Hardware support for real-time embedded multiprocessor system-on-a-chip memory management
Proceedings of the tenth international symposium on Hardware/software codesign
Cluster miss prediction for instruction caches in embedded networking applications
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Journal of VLSI Signal Processing Systems
Enabling unrestricted automated synthesis of portable hardware accelerators for virtual machines
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Exploration of distributed shared memory architectures for NoC-based multiprocessors
Journal of Systems Architecture: the EUROMICRO Journal
Science of Computer Programming
Memory-access-aware data structure transformations for embedded software with dynamic data accesses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)
Power aware data type refinement for the HIPERLAN/2
MIV'05 Proceedings of the 5th WSEAS international conference on Multimedia, internet & video technologies
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In embedded network applications, typically a very large part of the area cost is due to memory units. Also the power for such applications is heavily dominated by the storage and transfers. Given its importance, we have developed a systematic memory management methodology in which the storage related issues are optimized as a first step. In this paper, we present our methodology for embedded network applications. It includes both a dynamic memory management stage, where the data types and virtual memory managers are defined, and a physical memory management stage, where the custom memory architecture is defined. As demonstrated on an industrial example, the application of the methodology results in a heavily power and/or area optimized custom memory architecture for a given application