Power aware data type refinement for the HIPERLAN/2

Authors:
Gregory Dimitroulakos;Athanasios Milidonis;Michalis D. Galanis;Ch. Ykman-Couvreur;Athanassios Kakarountas;Francky Catthoor;Costas E. Goutis
Affiliations:
VLSI Design Laboratory, Electrical & Computer Engineering Department, University of Patras, Greece and Interuniversity Micro Electronics Center, Belguim;VLSI Design Laboratory, Electrical & Computer Engineering Department, University of Patras, Greece and Interuniversity Micro Electronics Center, Belguim;VLSI Design Laboratory, Electrical & Computer Engineering Department, University of Patras, Greece and Interuniversity Micro Electronics Center, Belguim;VLSI Design Laboratory, Electrical & Computer Engineering Department, University of Patras, Greece and Interuniversity Micro Electronics Center, Belguim;VLSI Design Laboratory, Electrical & Computer Engineering Department, University of Patras, Greece and Interuniversity Micro Electronics Center, Belguim;VLSI Design Laboratory, Electrical & Computer Engineering Department, University of Patras, Greece and Interuniversity Micro Electronics Center, Belguim;VLSI Design Laboratory, Electrical & Computer Engineering Department, University of Patras, Greece and Interuniversity Micro Electronics Center, Belguim
Venue:
MIV'05 Proceedings of the 5th WSEAS international conference on Multimedia, internet & video technologies
Year:
2005

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Abstract

This paper considers a domain specific methodology that has been employed to derive a cost optimized on-chip memory architecture for network protocols such as the Data Link Control layer of the HIPERLAN/2 protocol. The performed design flow was based on a well established methodology script which is appropriate for network protocol applications. The methodology consists of a sequence of steps that take as input the initial code specification. Initially the application's data types are identified automatically and then the crucial ones in terms of power are optimized. Finally, for the optimized code specification the methodology exctract as output an optimized on-chip memory architecture. During the optimization process, the time constraints are also taken into account as they are crucial in wireless network protocol applications. As the experimental results show, the application of the methodology on the HIPERLAN/2 application reduces the power consumption up to 37% comparing to that imposed by the initial code specification.