MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Measuring Cache and TLB Performance and Their Effect on Benchmark Runtimes
IEEE Transactions on Computers
Hardware support for real-time embedded multiprocessor system-on-a-chip memory management
Proceedings of the tenth international symposium on Hardware/software codesign
Predictable and Efficient Virtual Addressing for Safety-Critical Real-Time Systems
ECRTS '01 Proceedings of the 13th Euromicro Conference on Real-Time Systems
A Banked-Promotion TLB for High Performance and Low Power
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Compiler-directed code restructuring for reducing data TLB energy
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
An energy efficient TLB design methodology
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Synonymous address compaction for energy reduction in data TLB
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
The M5 Simulator: Modeling Networked Systems
IEEE Micro
| Hi-index | 0.00 |
We present a novel page table organization for real-time and memory-constrained embedded systems. Increasingly many high-end embedded processors offer virtual memory support in the form of hardware Memory Management Unit. To implement virtual memory support, however, the system software needs to maintain a page table per task, which captures the virtual to physical page translation information. Page tables have been traditionally designed for general-purpose systems where their size and real-time performance have not been of primary importance; the average performance of page table traversal has been the major concern. Many embedded systems, however, impose strict real-time requirements coupled with limited memory resources. To address this problem, we propose a new page table organization, which not only requires significantly less memory than the traditional page tables, but also enables a very fast and deterministic hardware-based page table lookup. This is achieved by exploiting application knowledge regarding the memory footprint of the program under execution.