An Efficient Deadlock Avoidance Technique
IEEE Transactions on Computers
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Some Deadlock Properties of Computer Systems
ACM Computing Surveys (CSUR)
Comments on prevention of system deadlocks
Communications of the ACM
Compact finite difference schemes for ocean models: 1. Ocean waves
Journal of Computational Physics
Operating System Concepts
Hardware support for real-time embedded multiprocessor system-on-a-chip memory management
Proceedings of the tenth international symposium on Hardware/software codesign
The system-on-a-chip lock cache
The system-on-a-chip lock cache
A Novel Deadlock Avoidance Algorithm and Its Hardware Implementation
CODES+ISSS '04 Proceedings of the international conference on Hardware/Software Codesign and System Synthesis: 2004
Hardware/software deadlock avoidance for multiprocessor multiresource system-on-a-chip
Hardware/software deadlock avoidance for multiprocessor multiresource system-on-a-chip
Cooperating Sequential Processes, Technical Report EWD-123
Cooperating Sequential Processes, Technical Report EWD-123
A novel O(n) parallel banker's algorithm for System-on-a-Chip
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Instant Multiunit Resource Hardware Deadlock Detection Scheme for System-on-Chips
ACM Transactions on Embedded Computing Systems (TECS)
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This article proposes a novel O(n) Parallel Banker's Algorithm (PBA), which is a parallelized version of the Banker's Algorithm (BA), a well-known O(m\times n) deadlock avoidance algorithm. We implement the approach in hardware, which we call PBA Unit (PBAU). PBAU is not a mere Verilog HDL translation of BA, but a novel, fully hardware-oriented implementation exploiting maximum hardware parallelism of all computations in BA, resulting in O(1) runtime complexity in the best case and O(n) in the worst. PBAU is an Intellectual Property (IP) block that provides a mechanism of very fast, automatic deadlock avoidance for Multiprocessor System-on-a-Chip (MPSoC), which we predict will be the mainstream of future high performance computing environments. Furthermore, our PBAU supports multiple instance multiple resource systems. We demonstrate that PBAU not only avoids deadlock in a few clock cycles (several orders of magnitude faster than BA in software), but also achieves, in a particular example, a 19 percent speedup of application execution time over avoiding deadlock in software. Lastly, the MPSoC area overhead due to PBAU is small, less than 0.05 percent in our candidate MPSoC example.