Store Memory-Level Parallelism Optimizations for Commercial Applications
Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
Two management approaches of the split data cache in multiprocessor systems
EURO-PDP'00 Proceedings of the 8th Euromicro conference on Parallel and distributed processing
Cache management for discrete processor architectures
ISPA'05 Proceedings of the Third international conference on Parallel and Distributed Processing and Applications
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In this paper a multiprocessor system with two-level cache hierarchy has been modeled and extensions of two write invalidate snoopy protocols have been implemented in the L2 cache controller for coherence maintenance. The paper focuses on the use of different techniques for reducing miss penalty and a comparative performance study has been done for each possibility. To solve efficiently a miss read, the early restart technique has been implemented inthe second level of cache hierarchy and the critical word first technique has been used in the first level cache controller. To obtain better performance in the case of a write miss the write allocate technique has been implemented at the L2 cache controller. Two models, with different L1 cache controllers has been considered in our study, one of them using the non write allocate technique and the other using the write allocate. We show that the write allocate and non write allocate techniques are independent over the processors number. The major conclusion of this work is that the non write allocate technique is not only less complex for implementing but also better in performance if the L1 write miss rate represent a high percentage of L1 miss rate.