Two management approaches of the split data cache in multiprocessor systems

Authors:
J. Sahuquillo;A. Pont
Affiliations:
Departamento de Informática de Sistemas y Computadores, Universidad Politécnica de Valencia, Valencia, Spain;Departamento de Informática de Sistemas y Computadores, Universidad Politécnica de Valencia, Valencia, Spain
Venue:
EURO-PDP'00 Proceedings of the 8th Euromicro conference on Parallel and distributed processing
Year:
2000

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Abstract

As processor speed continues, the gap between the processor cycle and the memory subsystem cycle is expected to grow. One solution to this growing problem is to maximize the first level (L1) cache hit ratio, therefore the mean memory access time can decrease. Several studies have been made in order to manage more efficiently the L1 data cache, both in uniprocessor both in multiprocessor systems. These studies seek two main objectives, to increase the L1 hit ratio and to reduce the chip area occupied by these caches. In this work we present two new different approaches for increasing the L1 hit ratio in multiprocessor systems and we compare with a conventional organization. Performance evaluation and hardware cost of these organizations are also calculated and compared with the cost incurred by the most common organization used.