A case of SCMP with TLS

Authors:
Jianzhuang Lu;Chunyuan Zhang;Zhiying Wang;Yun Cheng;Dan Wu
Affiliations:
School of Computer, National University of Defense Technology, Changsha, Hunan, China;School of Computer, National University of Defense Technology, Changsha, Hunan, China;School of Computer, National University of Defense Technology, Changsha, Hunan, China;School of Computer, National University of Defense Technology, Changsha, Hunan, China;School of Computer, National University of Defense Technology, Changsha, Hunan, China
Venue:
ISPA'04 Proceedings of the Second international conference on Parallel and Distributed Processing and Applications
Year:
2004

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Abstract

As an alternative way of chip design, Single Chip Multi-Processors (SCMP) has been a hot topic in microprocessor architecture research all the while. It achieves higher performance by extracting thread-level parallelism (TLP). Thread-level speculation (TLS) is an important way to simplify TLP extraction. This paper presents a new SCMP architecture called Griffon, which aims at general-purpose applications. It implements thread partition in assembly language. It supports thread-level speculation with simple logics and maintains data dependence using a dual-ring structure. Simulation and synthesis results show that Griffon can achieve ideal speedup, less design complexity and accessorial hardware cost.