CoreRacer: a practical memory race recorder for multicore x86 TSO processors

  • Authors:

  • Gilles Pokam;Cristiano Pereira;Shiliang Hu;Ali-Reza Adl-Tabatabai;Justin Gottschlich;Jungwoo Ha;Youfeng Wu

  • Affiliations:

  • Intel Corporation;Intel Corporation;Intel Corporation;Intel Corporation;Intel Corporation;Google;Intel Corporation

  • Venue:
  • Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
  • Year:
  • 2011

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Abstract

Shared memory multiprocessors are difficult to program because of the non-deterministic ways in which the memory operations from different threads interleave. To address this issue, many hardware-based memory race recorders have been proposed that efficiently log an ordering of the shared memory interleavings between threads for deterministic replay. These approaches are challenging to integrate into current processors because they change the cache subsystem or the coherence protocol, and they mostly support a sequentially consistent memory model. In this paper, we describe CoreRacer, a chunk-based memory race recorder architecture for multicore x86 TSO processors. CoreRacer does not modify the cache subsystem and yet it still integrates into the x86 TSO memory model. We show that by leveraging a specific x86 feature, the invariant timestamp, CoreRacer maintains ordering among chunks without piggybacking on cache coherence messages. We provide a detailed implementation and evaluation of CoreRacer on a cycle-accurate x86 simulator. We show that its integration cost into x86 is minimal and its overhead has negligible effect on performance.