An analytic framework for performance modeling of software transactional memory

Authors:
Armin Heindl;Gilles Pokam
Affiliations:
Computer Networks and Communication Systems, University of Erlangen-Nuremberg, Germany;Microprocessor Technology Lab, Intel Corporation, Santa Clara, CA, United States
Venue:
Computer Networks: The International Journal of Computer and Telecommunications Networking
Year:
2009

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Abstract

Analytic models based on discrete-time Markov chains (DTMC) are proposed to assess the algorithmic performance of Software Transactional Memory (TM) systems. Base STM variants are compared: optimistic STM with inplace memory updates and write buffering and pessimistic STM. Starting from an absorbing DTMC, closed-form analytic expressions are developed, which are quickly solved iteratively to determine key parameters of the considered STM systems, like the mean number of transaction restarts and the mean transaction length. Since the models reflect complex transactional behavior in terms of read/write locking, data consistency checks and conflict management independent of implementation details, they highlight the algorithmic performance advantages of one system over the other, which - due to their at times small differences - are often blurred by implementation of STM systems and even difficult to discern with statistically significant discrete-event simulations.