Transactional memory: architectural support for lock-free data structures
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Proceedings of the fourteenth annual ACM symposium on Principles of distributed computing
Software transactional memory for dynamic-sized data structures
Proceedings of the twenty-second annual symposium on Principles of distributed computing
Programming with transactional coherence and consistency (TCC)
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
Unbounded Transactional Memory
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
McRT-STM: a high performance software transactional memory system for a multi-core runtime
Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Unbounded page-based transactional memory
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Modeling optimistic concurrency using quantitative dependence analysis
Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming
Implications of False Conflict Rate Trends for Robust Software Transactional Memory
IISWC '07 Proceedings of the 2007 IEEE 10th International Symposium on Workload Characterization
An analytic framework for performance modeling of software transactional memory
Computer Networks: The International Journal of Computer and Telecommunications Networking
Modeling software transactional memory with AnyLogic
Proceedings of the 2nd International Conference on Simulation Tools and Techniques
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We extend an existing analytic framework for modeling software transactional memory (STM) to an optimistic STM variant in which write locks are acquired lazily. Lazy locking requires a different calculation of the transition probabilities of the underlying discrete-time Markov chain (DTMC). Based on few relevant input parameters, like the number of concurrent transactions, the transaction lengths, the share of writing operations and the number of accessible transactional data ojects, a fixed-point iteration over closed-form analytic expressions delivers key STM performance measures, e.g., the mean number of transaction restarts and the mean number of processed steps of a transaction. In particular, the analytic model helps to predict STM performance trends as the number of cores on multi-processors increases, but other performance trends provide additional insight into system behavior.