Performance Pathologies in Hardware Transactional Memory

Authors:
Jayaram Bobba;Kevin E. Moore;Haris Volos;Luke Yen;Mark D. Hill;Michael M. Swift;David A. Wood
Affiliations:
University of Wisconsin—Madison;Sun Microsystems;University of Wisconsin—Madison;University of Wisconsin—Madison;University of Wisconsin—Madison;University of Wisconsin—Madison;University of Wisconsin—Madison
Venue:
IEEE Micro
Year:
2008

Citing 0
Cited 2

An analytic framework for performance modeling of software transactional memory

Computer Networks: The International Journal of Computer and Telecommunications Networking
Extending concurrency of transactional memory programs by using value prediction

Proceedings of the 6th ACM conference on Computing frontiers

Quantified Score

Hi-index	0.00

Visualization

Abstract

Transactional memory is a promising approach to ease parallel programming. Hardware transactional memory system designs reflect choices along three key design dimensions: conflict detection, version management, and conflict resolution. The authors identify a set of performance pathologies that could degrade performance in proposed HTM designs. Improving conflict resolution could eliminate these pathologies so designers can build robust HTM systems.