Transactional memory: architectural support for lock-free data structures
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Universal classes of hash functions (Extended Abstract)
STOC '77 Proceedings of the ninth annual ACM symposium on Theory of computing
Transactional Memory Coherence and Consistency
Proceedings of the 31st annual international symposium on Computer architecture
Virtualizing Transactional Memory
Proceedings of the 32nd annual international symposium on Computer Architecture
Bulk Disambiguation of Speculative Threads in Multiprocessors
Proceedings of the 33rd annual international symposium on Computer Architecture
An effective hybrid transactional memory system with strong isolation guarantees
Proceedings of the 34th annual international symposium on Computer architecture
The transaction concept: virtues and limitations (invited paper)
VLDB '81 Proceedings of the seventh international conference on Very Large Data Bases - Volume 7
A Study of a Transactional Parallel Routing Algorithm
PACT '07 Proceedings of the 16th International Conference on Parallel Architecture and Compilation Techniques
LogTM-SE: Decoupling Hardware Transactional Memory from Caches
HPCA '07 Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture
Implementing Signatures for Transactional Memory
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
Amdahl's Law in the Multicore Era
Computer
Notary: Hardware techniques to enhance signatures
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Improving Signatures by Locality Exploitation for Transactional Memory
PACT '09 Proceedings of the 2009 18th International Conference on Parallel Architectures and Compilation Techniques
Transactional Memory, 2nd Edition
Transactional Memory, 2nd Edition
Multiset signatures for transactional memory
Proceedings of the international conference on Supercomputing
Unified Signatures for Improving Performance in Transactional Memory
IPDPS '11 Proceedings of the 2011 IEEE International Parallel & Distributed Processing Symposium
Application-specific signatures for transactional memory in soft processors
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
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Optimistic concurrency provided by Transactional Memory (TM) makes it a good candidate for maintaining synchronization in future multi-core processors. Speculative execution and bulk level conflict detection enable TM to provide synchronization at fine grain without the complexity of managing fine grain locks. Early hardware TM systems proposed to store the information needed for checking conflicts in the Level 1 (L1) cache, thereby limiting the size of a transaction to the size of the L1 cache. The introduction of signatures to TM systems removed this limitation and allowed transactions to be of any size. However signatures produce false positives which leads to performance degradation in TM systems. The objective of introducing signatures to TM is that the size of a transaction can be bigger than the L1 cache. Once signatures are integrated to a TM system, they are used to detect conflicts regardless of the size of a transaction. This means signatures are being used even for transactions that can store their read and write sets in the L1 cache. Based on this observation we propose SnCTM, a TM system that adaptively changes the source used to detect conflicts. In our approach, when a transaction fits in the L1 cache, cache line information is used to detect conflicts and signatures are used otherwise. By adaptively changing the source, SnCTM achieved up to 4.62 and 2.93 times speed-up over a baseline TM using lazy versioning and lazy conflict detection with two commonly used signature configurations. We also show that our system, even with a smaller signature (64 bit), can achieve performance comparable to a system with a perfect signature (8k bit).