Experiences using adaptive concurrency in transactional memory with Lee's routing algorithm
Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming
A first insight into object-aware hardware transactional memory
Proceedings of the twentieth annual symposium on Parallelism in algorithms and architectures
Lee-TM: A Non-trivial Benchmark Suite for Transactional Memory
ICA3PP '08 Proceedings of the 8th international conference on Algorithms and Architectures for Parallel Processing
Advanced Concurrency Control for Transactional Memory Using Transaction Commit Rate
Euro-Par '08 Proceedings of the 14th international Euro-Par conference on Parallel Processing
An efficient transactional memory algorithm for computing minimum spanning forest of sparse graphs
Proceedings of the 14th ACM SIGPLAN symposium on Principles and practice of parallel programming
Steal-on-Abort: Improving Transactional Memory Performance through Dynamic Transaction Reordering
HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
Aspect-oriented support for synchronization in parallel computing
Proceedings of the 1st workshop on Linking aspect technology and evolution
Discovering and understanding performance bottlenecks in transactional applications
Proceedings of the 19th international conference on Parallel architectures and compilation techniques
Lightweight software transactions for games
HotPar'09 Proceedings of the First USENIX conference on Hot topics in parallelism
Scalable object-aware hardware transactional memory
EuroPar'10 Proceedings of the 16th international Euro-Par conference on Parallel processing: Part I
Efficient and Deterministic Parallel Placement for FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Robust adaptation to available parallelism in transactional memory applications
Transactions on high-performance embedded architectures and compilers III
A study of transactional memory vs. locks in practice
Proceedings of the twenty-third annual ACM symposium on Parallelism in algorithms and architectures
Hardware transactional memory with software-defined conflicts
ACM Transactions on Architecture and Code Optimization (TACO) - HIPEAC Papers
SnCTM: reducing false transaction aborts by adaptively changing the source of conflict detection
Proceedings of the 9th conference on Computing Frontiers
Optimizing software runtime systems for speculative parallelization
ACM Transactions on Architecture and Code Optimization (TACO) - Special Issue on High-Performance Embedded Architectures and Compilers
Unifying thread-level speculation and transactional memory
Proceedings of the 13th International Middleware Conference
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Transactional memory proposes an alternative synchronization primitive to traditional locks. Its promise is to simplify the software development of multi-threaded applications while at the same time delivering the performance of parallel applications using (complex and error prone) fine grain locking. This study reports our experience implementing a realistic application using transactional memory (TM). The application is Lee's routing algorithm and was selected for its abundance of parallelism but difficulty of expressing it with locks. Each route between a source and a destination point in a grid can be considered a unit of parallelism. Starting from this simple approach, we evaluate the exploitable parallelism of a transactional parallel implementation and explore how it can be adapted to deliver better performance. The adaptations do not introduce locks nor alter the essence of the implemented algorithm, but deliver up to 20 times more parallelism. The adaptations are derived from understanding the application itself and TM. The evaluation simulates an abstracted TM system and, thus, the results are independent of specific software or hardware TM implemented, and describe properties of the application.