Energy and throughput efficient transactional memory for embedded multicore systems

Authors:
Cesare Ferri;Samantha Wood;Tali Moreshet;Iris Bahar;Maurice Herlihy
Affiliations:
Division of Engineering, Brown University, Providence;Division of Engineering, Brown University, Providence;Engineering Department, Swarthmore College, Swarthmore;Division of Engineering, Brown University, Providence;Computer Science Department, Brown University, Providence
Venue:
HiPEAC'10 Proceedings of the 5th international conference on High Performance Embedded Architectures and Compilers
Year:
2010

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Abstract

We propose a new design for an energy-efficient hardware transactional memory (HTM) system for power-aware embedded devices. Prior hardware transactional memory designs proposed a small, fully-associative transactional cache at the same level as the L1 cache. We propose an alternative design that unifies the transactional and L1 caches, and provides a small victim cache to reduce effects of capacity and conflict evictions. We evaluate our new HTM scheme on a variety of benchmarks, both in terms of energy and performance. We show that the victim cache scheme can provide up to a 4X improvement in energy-delay product, compared to a traditional HTM scheme that uses a separate transactional cache.