Evaluation of a hardware transactional memory model in an NoC-based embedded MPSoC

  • Authors:
  • Leonardo Kunz;Gustavo Girão;Flávio R. Wagner

  • Affiliations:
  • Federal University of Rio Grande do Sul, Porto Alegre, Brazil;Federal University of Rio Grande do Sul, Porto Alegre, Brazil;Federal University of Rio Grande do Sul, Porto Alegre, Brazil

  • Venue:
  • SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
  • Year:
  • 2010

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Abstract

Transactional memories have emerged in the last years as a new solution for synchronization on shared memory multiprocessors helping to exploit the parallelism of applications while overcoming limitations of the lock mechanism. This paper presents the performance and energy evaluation of a hardware transactional memory (HTM) solution in an NoC-based MPSoC environment, comparing it to a traditional shared memory model that uses locks to provide consistency. Experiments show that transactional memory is a promising alternative to locks for future NoC-based embedded systems, resulting in performance gains up to 30% and energy savings up to 32%, depending on the application and on the architecture configuration.