A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
SPIN: A Scalable, Packet Switched, On-Chip Micro-Network
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
ParIS: a parameterizable interconnect switch for networks-on-chip
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
A Complete Network-On-Chip Emulation Framework
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
LiPaR: A light-weight parallel router for FPGA-based networks-on-chip
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Improving routing efficiency for network-on-chip through contention-aware input selection
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
DNCOCO'07 Proceedings of the 9th WSEAS International Conference on Data Networks, Communications, Computers
Modeling and Implementation of an Output-Queuing Router for Networks-on-Chips
ICESS '07 Proceedings of the 3rd international conference on Embedded Software and Systems
Proceedings of the 7th ACM international conference on Computing frontiers
A Low-Latency and Memory-Efficient On-chip Network
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Evaluation of a hardware transactional memory model in an NoC-based embedded MPSoC
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
Proceedings of the Conference on Design, Automation and Test in Europe
Journal of Electronic Testing: Theory and Applications
Dynamic clustering for distinct parallel programming models on NoC-based MPSoCs
Proceedings of the 4th International Workshop on Network on Chip Architectures
A simple and efficient input selection function for networks-on-chip
ICDCN'12 Proceedings of the 13th international conference on Distributed Computing and Networking
Exploring resource mapping policies for dynamic clustering on NoC-based MPSoCs
Proceedings of the Conference on Design, Automation and Test in Europe
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The building block of a Network-on-Chip (NoCs) is its router. It is responsible to switch the channels which forward the messages exchanged by the cores attached to the NoC, and the costs and performance of the NoC strongly depends on the router architecture. In this paper, we present RASoC, a router architecture intended to be used in the building of low area overhead NoCs for embedded systems. The difference among RASoC and current routers relies on its implementation as a parameterized VHDL model, which improve the reuse of RASoC in the synthesis of NoCs with different sizes, and allows the tuning of the NoC parameters in order to meet the requirements of the target application. The paper presents details of RASoC architecture, the structure of the VHDL model and some experimental results which show the scalability of the soft-core and its costs.