Modeling and Implementation of an Output-Queuing Router for Networks-on-Chips

Authors:
Haytham Elmiligi;M. Watheq El-Kharashi;Fayez Gebali
Affiliations:
Department of Electrical and Computer Engineering, University of Victoria, P.O. Box 3055 STN CSC, BC, V8W 3P6, Canada;Department of Computer and Systems Engineering, Ain Shams University, Cairo, Egypt;Department of Electrical and Computer Engineering, University of Victoria, P.O. Box 3055 STN CSC, BC, V8W 3P6, Canada
Venue:
ICESS '07 Proceedings of the 3rd international conference on Embedded Software and Systems
Year:
2007

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Abstract

Routers are pivotal modules in any networks-on-chip (NoC)-based design. In order to achieve an efficient router design, the size of the queue must be optimally chosen. The choice of queue size affects packet loss probability and impacts the silicon area of the overall NoC-based design. For these reasons, a modeling process is needed to obtain an early estimation of the optimum queue size that matches packet arrival rate, number of traffic sources, and the permissable loss probability. In this paper, we use Markov chain analysis to model an M/D/1/B queue for an NoC output-queuing router. We explain how to optimally chose the queue size using pre-defined design parameters that match different target applications. Our model is validated with a prototype router implementation on FPGA.