iPSC/2 system: a second generation hypercube
C3P Proceedings of the third conference on Hypercube concurrent computers and applications: Architecture, software, computer systems, and general issues - Volume 1
Express Cubes: Improving the Performance of k-ary n-cube Interconnection Networks
IEEE Transactions on Computers
The turn model for adaptive routing
Journal of the ACM (JACM)
Impact of selection functions on routing algorithm performance in multicomputer networks
ICS '97 Proceedings of the 11th international conference on Supercomputing
The Odd-Even Turn Model for Adaptive Routing
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Computers
IEEE Transactions on Parallel and Distributed Systems
Deadlock-Free Adaptive Routing in Multicomputer Networks Using Virtual Channels
IEEE Transactions on Parallel and Distributed Systems
A Necessary and Sufficient Condition for Deadlock-Free Adaptive Routing in Wormhole Networks
IEEE Transactions on Parallel and Distributed Systems
On the Influence of the Selection Function on the Performance of Networks of Workstations
ISHPC '00 Proceedings of the Third International Symposium on High Performance Computing
RASoC: A Router Soft-Core for Networks-on-Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 3
System-Level Design Techniques for Energy-Efficient Embedded Systems
System-Level Design Techniques for Energy-Efficient Embedded Systems
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
DyAD: smart routing for networks-on-chip
Proceedings of the 41st annual Design Automation Conference
A low latency router supporting adaptivity for on-chip interconnects
Proceedings of the 42nd annual Design Automation Conference
Improving routing efficiency for network-on-chip through contention-aware input selection
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
DyXY: a proximity congestion-aware deadlock-free dynamic routing method for network on chip
Proceedings of the 43rd annual Design Automation Conference
Express virtual channels: towards the ideal interconnection fabric
Proceedings of the 34th annual international symposium on Computer architecture
Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip
IEEE Transactions on Computers
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Wormhole-switching and virtual channel flow control are two critical techniques in networks-on-chip (NoCs). In an NoC adopting these two techniques, a packet may hold several virtual channel (vc) resources spanning multiple routers. These vcs constitute a vc chain to the packet. Through observation, we find that the lengths of the vc chains play an important role in the performance of an NoC, and it helps to improve the performance of the network to cut short the vc chains. In this paper, we propose a novel input selection function (ISF) which allows packets spanning in the network in a more compact and consecutive manner, thereby lowering the delay while simultaneously boosting throughput. Owing to the simplicity of the novel ISF, we can implement it with a practical design, incurring a minimal hardware overhead with an additional requirement of storage less than 3.6%. We simulate and evaluate the proposed input selection approach in terms of average delay and throughput. Our experimental results indicate that the proposed ISF is effective in NoC design compared to other ISFs in previous literatures. Though we assume a two-dimensional mesh topology throughout this paper, the proposed ISF can be readily extended to other topologies. Furthermore, it can be coupled with any OSF and any routing algorithm.