Transactional memory: architectural support for lock-free data structures
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Speculative lock elision: enabling highly concurrent multithreaded execution
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Transactional lock-free execution of lock-based programs
Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
Journal of Parallel and Distributed Computing
Evaluation of a hardware transactional memory model in an NoC-based embedded MPSoC
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
SoC-TM: integrated HW/SW support for transactional memory programming on embedded MPSoCs
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Proceedings of the 49th Annual Design Automation Conference
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High-end embedded systems such as smart phones, game consoles, GPS-enabled automotive systems, and home entertainment centers, are becoming ubiquitous. Like their general-purpose counterparts, and for many of the same energy-related reasons, embedded systems are turning to multicore architectures. Moreover, as the demand for more compute-intensive capabilities for embedded systems increases, these multicore architectures will evolve into many-core systems for improved performance or performance/area/Watt. These systems are often organized as cluster based Non-Uniform Memory Access (NUMA) architectures that provide the programmer with a shared-memory abstraction, with the cost of sharing memory (in terms of performance, energy, and complexity) varying substantially depending on the locations of the communicating processes. This paper investigates one of the principal challenges presented by these emerging NUMA architectures for embedded systems: providing efficient, energy-effective and convenient mechanisms for synchronization and communication. In this paper, we propose an initial solution based on hardware support for speculative synchronization.