Cache coherency communication cost in a NoC-based MPSoC platform

Authors:
Gustavo Girão;Bruno Cruz de Oliveira;Rodrigo Soares;Ivan Saraiva Silva
Affiliations:
Universidade Federal do Rio Grande do Norte, Natal, Brazil;Universidade Federal do Rio Grande do Norte, Natal, Brazil;Universidade de São Paulo, São Paulo, Brazil;Universidade Federal do Rio Grande do Norte, Natal, Brazil
Venue:
Proceedings of the 20th annual conference on Integrated circuits and systems design
Year:
2007

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Abstract

Cache coherency and cache consistency in NoC-based heterogeneous platforms are still open problems. Current works addressing platform design avoid this issue either by proposing cacheless implementations or using snoopy protocols over buses. This paper addresses the cache coherence problem in a NoC-based MPSoC platform, focusing the communication considering both the load overhead produced by the coherency mechanism and read/write response times. Simulations of applications written in C and compiled with GCC are presented. Simulations results indicate that the load is constant with the cache size for a given line size.