DAC '96 Proceedings of the 33rd annual Design Automation Conference
A generic wrapper architecture for multi-processor SoC cosimulation and design
Proceedings of the ninth international symposium on Hardware/software codesign
Proceedings of the 38th annual Design Automation Conference
Parallel Computer Architecture: A Hardware/Software Approach
Parallel Computer Architecture: A Hardware/Software Approach
A low-overhead coherence solution for multiprocessors with private cache memories
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs
Proceedings of the 42nd annual Design Automation Conference
Cache coherency communication cost in a NoC-based MPSoC platform
Proceedings of the 20th annual conference on Integrated circuits and systems design
Extending open core protocol to support system-level cache coherence
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
A tuneable software cache coherence protocol for heterogeneous MPSoCs
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Building heterogeneous reconfigurable systems with a hardware microkernel
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Ordering decoupled metadata accesses in multiprocessors
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Exploring memory organization in virtual MP-SoC platforms
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
Pseudo share data cache in multiprocessor: PSDMP
ISPA'06 Proceedings of the 2006 international conference on Frontiers of High Performance Computing and Networking
Energy and performance exploration of accelerator coherency port using Xilinx ZYNQ
Proceedings of the 10th FPGAworld Conference
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In embedded system-on-a-chip (SoC) applications, the demand for integrating heterogeneous processors onto a single chip is increasing. An important issue in integrating multiple heterogeneous processors on the same chip is to maintain the coherence of their data caches. In this paper, we propose a hardware/software methodology to make caches coherent in heterogeneous multiprocessor platforms with shared memory. Our approach works with any combination of processors that support invalidation-based protocols. As shown in our experiments, up to 58% performance improvement can be achieved with low miss penalty at the expense of adding simple hardware, compared to a pure software solution. Speedup can be improved even further as the miss penalty increases. In addition, our approach provides embedded system programmers a transparent view of shared data, removing the burden of software synchronization.