Integrating Cache Coherence Protocols for Heterogeneous Multiprocessor Systems, Part 1

Authors:
Taeweon Suh;Hsien-Hsin S. Lee;Douglas M. Blough
Affiliations:
Georgia Institute of Technology;Georgia Institute of Technology;Georgia Institute of Technology
Venue:
IEEE Micro
Year:
2004

Citing 9
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Integrating Cache Coherence Protocols for Heterogeneous Multiprocessor Systems, Part 2

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Abstract

This systematic methodology maintains cache coherency in a heterogeneous shared-memory multiprocessor system on a chip. It works with any combination of processors that support any invalidation-based protocol, and experiments have demonstrated up to a 51 percent performance improvement, compared to a pure software solution.