Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs

Authors:
Taeweon Suh;Daehyun Kim;Hsien--Hsin S. Lee
Affiliations:
Georgia Institute of Technology, Atlanta, GA;Intel Corporation, Santa Clara, CA;Georgia Institute of Technology, Atlanta, GA
Venue:
Proceedings of the 42nd annual Design Automation Conference
Year:
2005

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Abstract

We propose two novel integration techniques ̬ bypass and bookkeeping̬in the memory controller to address the cache coherence compatibility issue of a non-shared bus heterogeneous MPSoC. The bypass approach is an inexpensive and efficient solution for computation-bound applications while the bookkeeping approach eliminating unnecessary forwarding traffic offers an alternative for bandwidth-limited applications. Our RTOS kernel simulations show up to 6.65x speedup over the conventional software solution.