Location Consistency-A New Memory Model and Cache Consistency Protocol
IEEE Transactions on Computers
Specifying and Verifying a Broadcast and a Multicast Snooping Cache Coherence Protocol
IEEE Transactions on Parallel and Distributed Systems
Supporting Cache Coherence in Heterogeneous Multiprocessor Systems
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Multi-log Processor - Towards Scalable Event-Driven Multiprocessors
DSD '04 Proceedings of the Digital System Design, EUROMICRO Systems
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With the development of semiconductor technology, multicore is integrated on one chip [1]. In CMP, more than one core accessing the shared data will cause memory access conflict and the problem of cache coherence. Cache coherence is a precondition for the system to function correctly. So it is a key problem in CMP. In this paper, we propose a new pseudo sharing level one data cache in a chip multiprocessor architecture (PSDMP). In PSDMP, the request of memory access will be propagated on a ring chain. This method can reduce both the complexity of the design and the load of L2 cache. Simulation results show that performance of PSDMP improves about 30% averagely than another CMP which uses MESI protocol, especially the best is about 100% for the parallel applications which has many inter-processor communications for modifying shared data. In one word, PSDMP is promising processor architecture.