When reconfigurable architecture meets network-on-chip

Authors:
Rodrigo Soares;Ivan Saraiva Silva;Arnaldo Azevedo
Affiliations:
Universidade Federal do Rio Grande do Norte, Natal - Brasil;Universidade Federal do Rio Grande do Norte, Natal - Brasil;Universidade Federal do Rio Grande do Sul, Porto Alegre - Brasil
Venue:
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Year:
2004

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Abstract

This paper analyzes the utilization of a network on chip (NoC) as the communication sub-system of a reconfigurable/parallel architecture. A router was designed and implemented in SystemC to analyze the NoC. With this routers the NoCX4 was created and simulated using coarse-grained reconfigurable microprocessor as processing nodes. To perform the simulation two approaches were used. The first one uses a load generator program and communication loads between 5% and 25%. The second is the calculation of 2D-DCT coefficients.