When reconfigurable architecture meets network-on-chip
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
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The X4CP32 is a parallel/reconfigurable microprocessor with 2 programming levels. Although itis a general-purpose microprocessor, it has the reliable performance of a reconfigurable architecture. This paper exposes its architecture and programming levels, and discusses the powerful interaction between parallel programming and reconfiguration. It shows twoperformance-optimized implementations of matrix multiplication using both parallel and reconfigurable paradigms and a parallel implementation of miner intelligent agents.