Low-Latency Asynchronous FIFO's Using Token Rings
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Delay Insensitive System-on-Chip Interconnect using 1-of-4 Data Encoding
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
MOUSETRAP: Ultra-High-Speed Transition-Signaling Asynchronous Pipelines
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
When reconfigurable architecture meets network-on-chip
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
GALDS: a complete framework for designing multiclock ASICs and socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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An architecture that combines a Globally Asynchronous, Locally Synchronous (GALS) [1,2] design style with dynamic voltage and frequency scaling can use the slowest frequency possible to accomplish a task with minimum power consumption. The proposed Globally Asynchronous, Locally Dynamic System (GALDS) requires three distinct components: a novel bidirectional asynchronous FIFO to communicate between independently-clocked synchronous blocks [3], an all-digital dynamic clock generator to quickly and glitchlessly switch between frequencies and a digitally-controlled oscillator to generate global fixed frequency clocks required by the all-digital dynamic clock generator. These circuits have been designed and simulated for all the tasks required to implement a complete GALDS infrastructure. The architecture is easily scaled due to the modular nature of these circuits and is useful for a wide range of applications.