The simulation and evaluation of dynamic voltage scaling algorithms
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Modeling and comparing CMOS implementations of the C-element
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Lowering power consumption in clock by using globally asynchronous locally synchronous design style
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Pausible clocking-based heterogeneous systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Interfacing synchronous and asynchronous modules within a high-speed pipeline
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 11th international symposium on system-level synthesis and design (ISSS'98)
Robust interfaces for mixed-timing systems with application to latency-insensitive protocols
Proceedings of the 38th annual Design Automation Conference
Introduction to VLSI Systems
Area Time Trade-Offs in Micro-Grain VLSI Array Architectures
IEEE Transactions on Computers
Pausible Clocking: A First Step Toward Heterogeneous Systems
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
A globally asynchronous locally dynamic system for ASICs and SoCs
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Optimal buffered routing path constructions for single and multiple clock domain systems
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Low-Latency Asynchronous FIFO's Using Token Rings
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Delay Insensitive System-on-Chip Interconnect using 1-of-4 Data Encoding
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
Point to Point GALS Interconnect
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Efficient Self-Timed Interfaces for Crossing Clock Domains
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Fourteen Ways to Fool Your Synchronizer
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Timing Measurements of Synchronization Circuits
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Energy Efficient Datapath Synthesis Using Dynamic Frequency Clocking and Multiple Voltages
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
On the Transistor Sizing Problem
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Advanced Synchronous Scan Test Methodology for Multi Clock Domain ASICs
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Clock Power Issues in System-on-a-Chip Designs
WVLSI '99 Proceedings of the IEEE Computer Society Workshop on VLSI'99
Profile-based dynamic voltage and frequency scaling for a multiple clock domain microprocessor
Proceedings of the 30th annual international symposium on Computer architecture
Dynamic voltage scaling algorithm for fixed-priority real-time systems using work-demand analysis
Proceedings of the 2003 international symposium on Low power electronics and design
HPCA '02 Proceedings of the 8th International Symposium on High-Performance Computer Architecture
MOUSETRAP: Ultra-High-Speed Transition-Signaling Asynchronous Pipelines
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Determining Schedules for Reducing Power Consumption Using Multiple Supply Voltages
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
A Dynamic Voltage Scaling Algorithm for Sporadic Tasks
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
Design of a Low Power Image Watermarking Encoder Using Dual Voltage and Frequency
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Power minimization by clock root gating
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Optimal path routing in single- and multiple-clock domain systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A linear array processor with dynamic frequency clocking for image processing applications
IEEE Transactions on Circuits and Systems for Video Technology
Two-level microprocessor-accelerator partitioning
Proceedings of the conference on Design, automation and test in Europe
Clock-frequency assignment for multiple clock domain systems-on-a-chip
Proceedings of the conference on Design, automation and test in Europe
A Survey and Taxonomy of GALS Design Styles
IEEE Design & Test
Trend and Challenge on System-on-a-Chip Designs
Journal of Signal Processing Systems
From synchronous to GALS: A new architecture for FPGAs
Microelectronics Journal
Power, interface, and integration: handset chipset design issues
IEEE Communications Magazine
Oversampled multi-phase time-domain bit-error rate processing for transmitter testing
Analog Integrated Circuits and Signal Processing
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A Globally Asynchronous, Locally Synchronous (GALS) system with dynamic voltage and frequency scaling can use the slowest frequency possible to accomplish a task with minimal power consumption. With the mechanism for implementing dynamic voltage scaling at each synchronous domain left up to the designer, our Globally Asynchronous, Locally Dynamic System (GALDS) provides a top-down, system-level means to maximize power reduction in an integrated circuit and facilitate system-on-a-chip (SoC) design. Our solution includes three distinct components: a novel bidirectional asynchronous FIFO to communicate between independently clocked synchronous blocks [5], an all-digital dynamic clock generator to quickly and glitchlessly switch between frequencies and a digitally controlled oscillator to generate the global fixed frequency clocks required by the all-digital dynamic clock generator. In addition to being capable of reducing power consumption when combined with dynamic voltage scaling, a GALDS design benefits from numerous other advantages such as simplified clock distribution, high performance operation and faster time-to-market through the modular nature of the architecture.