A Multiple-Valued Reed-Muller Transform for Incompletely Specified Functions
IEEE Transactions on Computers
Implementation of an Economic Jitter Compliance Test for a Multi-Gigabit Device on ATE
ITC '04 Proceedings of the International Test Conference on International Test Conference
ITC '04 Proceedings of the International Test Conference on International Test Conference
Optimization of imprecise circuits represented by Taylor series and real-valued polynomials
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Accelerating Test, Validation and Debug of High Speed Serial Interfaces
Accelerating Test, Validation and Debug of High Speed Serial Interfaces
GALDS: a complete framework for designing multiclock ASICs and socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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High speed serial interfaces (HSSI) are continually pushed toward operating at higher speed to meet the demand for higher bandwidth. As a result, the timing constraints for HSSI devices get tighter. Consequently, HSSI devices experience issues such as timing jitter and bit-errors. This paper investigates techniques to speed up HSSI bit-error rate and jitter testing. The proposed oversampling-based transmitter test scheme accelerates transmitter jitter and eye diagram testing by means of a multi-phase bit-error rate test circuit (BERT). The proposed scheme creates parallel BERT elements working in conjunction that are able to digitize the input signal jitter behavior in a multi-phase manner. The more phases we deploy the faster the test is completed. We accurately extract the transmitter jitter in time domain and finish the whole transmitter test within tens of milliseconds, exceeding the current norm of 100 ms.