GALDS: a complete framework for designing multiclock ASICs and socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we propose an energy efficient synthesis technique for datapath circuits. Specifically, we propose a time and resource constrained scheduling algorithm, (DFMVS), which utilizes the concept of Dynamic Frequency Clocking and Multiple Voltage Scaling. In the dynamic frequency scheme, all units are driven by a single clock line which changes at run time depending on the functional unit active at that time. Recently, the use of multiple voltages has been investigated in the context of energy minimization. DFMVS consists of two modules: Dynamic_freq_sched and Modify_sched. Based on the dynamic frequency scheme, Dynamic_freq_sched generates an initial schedule in which the control steps are clocked at different frequencies. Modify_sched incorporates a schedule modifier, that regroups the operations of the initial schedule such that multiple voltages can be used to reduce the energy consumption. The algorithm has been applied to various high level synthesis benchmark circuits under different time and resource constraints. The experimental results show that using three supply voltage levels (5.0V, 3.3V, 2.4V), an average energy saving of 53.5% (with the time constraint of 2.0 times the critical path) is obtained as compared to using a uni-frequency clocking scheme with a single supply voltage.