Configurable hardware: two case studies of micro-grain computation
Journal of VLSI Signal Processing Systems
Building and Using a Highly Parallel Programmable Logic Array
Computer - Special issue on experimental research in computer architecture
A Two-Dimensional, Distributed Logic Architecture
IEEE Transactions on Computers
SPAA '92 Proceedings of the fourth annual ACM symposium on Parallel algorithms and architectures
Parallel Supercomputing in SIMD Architectures
Parallel Supercomputing in SIMD Architectures
Content Addressable Parallel Processors
Content Addressable Parallel Processors
Programmable Systolic Arrays
GALDS: a complete framework for designing multiclock ASICs and socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We study the relative performance of three different massively parallel fine-grain, VLSI, control-flow architectures. The processor architectures being considered are: an associative memory architecture, a Mux-based SIMD architecture and a modification of the Mux-based architecture using RAMs making it suitable for systolic MIMD/MISD computation. All three architectures are organized as two-dimensional, near-neighbor mesh connected, array of processors. All three are very similar in their construction, and in their control and data-flow requirements. The custom hardware for all three architectures was built using the same technology. We compare and contrast the performance of these three VLSI architectures for a select set of applications. To evaluate the computational power of the three architectures we use the area time product, AT, as the metric. The three designs are known to perform well in their niche applications and we find that for non-niche applications all three designs are comparable in power to within a small constant factor. The performance of the Mux-based SIMD architecture is better in general than the other two in terms of speed though the associative architecture is found to out-perform the SIMD architecture for certain numeric applications like the FFT and matrix multiplication in the AT sense.