A globally asynchronous locally dynamic system for ASICs and SoCs
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Robust interfaces for mixed-timing systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A lattice-based framework for the classification and design of asynchronous pipelines
Proceedings of the 42nd annual Design Automation Conference
Performance driven reliable link design for networks on chips
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
An architecture and a wrapper synthesis approach for multi-clock latency-insensitive systems
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Design and DfT of a high-speed area-efficient embedded asynchronous FIFO
Proceedings of the conference on Design, automation and test in Europe
Self-resetting latches for asynchronous micro-pipelines
Proceedings of the 44th annual Design Automation Conference
MOUSETRAP: high-speed transition-signaling asynchronous pipelines
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An accelerator design for speedup of Java execution in consumer mobile devices
Computers and Electrical Engineering
Multi-Clock Latency-Insensitive Architecture and Wrapper Synthesis
Electronic Notes in Theoretical Computer Science (ENTCS)
Building asynchronous routers with independent sub-channels
SOC'09 Proceedings of the 11th international conference on System-on-chip
A low latency wormhole router for asynchronous on-chip networks
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
GALDS: a complete framework for designing multiclock ASICs and socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Abstract: A new asynchronous pipeline design is introduced for high-speed applications. The pipeline uses simple transparent latches in its datapath, and small latch controllers consisting of only a single gate per pipeline stage. This simple stage structure is combined with an efficient transition-signaling protocol between stages. Initial pre-layout HSPICE simulations of a 10-stage FIFO on a 16-bit wide datapath indicate throughput of 3.51 GigaHertz in 0.25µ CMOS, using a conservative process. This performance is competitive even with that of wave pipelines [25, 11, 14], with-out the accompanying problems of complex timing and much de-sign effort. Additionally, the new pipeline gracefully and robustly adapts to variable-speed environments. The stage implementations are extended to fork and join structures, to handle more complex system architectures.