The Counterflow Pipeline Processor Architecture
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This paper introduces a novel approach to efficiently implement several useful architectural features in asynchronous application-specific ICs (ASICs). These features include speculation, preemption, and eager evaluation, which have so far only been available on CPUs, and have not been adequately investigated for custom ASICs. For the efficient implementation of the new architectural features, a radically new approach inspired by Sproull's counterflow pipelines [7] is proposed. The key idea is to allow special commands, called anti-tokens, to be propagated in a direction opposite to that of data, allowing certain computations to be killed before they are completed, if their results are no longer required. The net impact is a significant improvement in the throughput of a certain class of systems---e.g., those involving conditional computation---where a bottleneck pipeline stage can often be preempted if its result is determined to be no longer needed. Experimental results indicate that our approach can improve the system throughput by a factor of up to 2.2x, along with an energy savings of up to 27%.