Communications of the ACM
Self-timed rings and their application to division
Self-timed rings and their application to division
Four-phase micropipeline latch control circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automatic synthesis and optimization of partially specified asynchronous systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
High-Level Modeling and Design of Asynchronous Interface Logic
IEEE Design & Test
Projection: A Synthesis Technique for Concurrent Systems
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
High-Speed QDI Asynchronous Pipelines
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
The Design of an Asynchronous MIPS R3000 Microprocessor
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
Fine-Grain Pipelined Asynchronous Adders for High-Speed DSP Applications
WVLSI '00 Proceedings of the IEEE Computer Society Annual Workshop on VLSI (WVLSI'00)
MOUSETRAP: Ultra-High-Speed Transition-Signaling Asynchronous Pipelines
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a unifying framework for the modeling of asynchronous pipeline circuits. A pipeline protocol is captured in a graph-based model which defines the partial ordering of both its control and data events. The relationship between an entire space of different protocols is then captured in a semi-lattice, which has well-defined top and bottom elements, corresponding to the most concurrent and least concurrent protocol variants, respectively. This framework also provides a set of correct-by-construction transformation rules which allows for the systematic exploration of the entire design space by their successive application. To the best of our knowledge, this is the first formal framework for asynchronous pipelines which can capture protocols from a variety of logic style families, including both dynamic and static. It is also the first to provide a formal foundation for the design-space exploration of asynchronous pipelines.