Logic design principles with emphasis on testable semicustom circuits
Logic design principles with emphasis on testable semicustom circuits
Automatic generation of synchronous test patterns for asynchronous circuits
DAC '97 Proceedings of the 34th annual Design Automation Conference
Synchronous Test Generation Model for Asynchronous Circuits
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Multi-frequency wrapper design and optimization for embedded cores under average power constraints
Proceedings of the 42nd annual Design Automation Conference
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Power-aware SoC test planning for effective utilization of port-scalable testers
ACM Transactions on Design Automation of Electronic Systems (TODAES)
GALDS: a complete framework for designing multiclock ASICs and socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Wrapper design for multifrequency IP cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Vlsi integrated circuits like complex ASICs and SOCs often require a multi clock design style for functional and/or performance reasons. Especially in telecom applications there are often many complex clock structures and clock domain transitions necessary. This requirement complicates the generation of structured test programs (Scan/ATPG, BIST) with current known methods. Results are lots of test vectors which lead to long CPU and tester times for pattern generation, simulation and test application. Much effort is needed to generate skew insensitive test programs and verify them.This article describes a new approach of scan test implementation and generation of test programs for multi clock systems. By addition of a small and simple test circuit with standard library elements a almost push button solution is now possible. Effort for test program generation, CPU and tester time is reduced significantly. By use of a simple timeset, skew problems are eliminated since the circuit is fully synchonously tested by a two phase clocking scheme.