Logic design principles with emphasis on testable semicustom circuits
Logic design principles with emphasis on testable semicustom circuits
Advanced Synchronous Scan Test Methodology for Multi Clock Domain ASICs
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
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For ASICs/SOCs/ICs it is often very important to have an easy accessible delay measurement path for several reasons. The delay of a long path running across the whole chip through lots of instances (inverters, MUXes) makes it possible to measure the final process parameters of an ASIC/IC within the best and worst case production process window. This information is very important for production testing and assembly at the vendor site. But very often this information is also necessary at circuit pack level, system test level and even in the field - when in case of problems (functionality, timing, debugging) it should be known which "quality level" the ASIC/IC device has reached. Also for characterization of the delay modeling during the different design phases (estimation, floorplanning, trial and final layout) such a dedicated delay path may help in qualifying the delay models together with the topological information of the database. We propose to use a new standard methodology to address these issues by definition of a dedicated delay path. It is called "Boundary Scan Delay Chain" (BSDC). We use the Boundary Scan data register according IEEE1149.1 to get a delay chain across the chip. Only a slight modification of the boundary scan cells (e.g. BC_1, BC_4) is necessary. The resulting new functionality is still IEEE1149.1 conform.