Limits of instruction-level parallelism
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Hardware/software partitioning for multi-function systems
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Task scheduling and voltage selection for energy minimization
Proceedings of the 39th annual Design Automation Conference
Hardware-Software Cosynthesis for Digital Systems
IEEE Design & Test
An Online Algorithm for Segmenting Time Series
ICDM '01 Proceedings of the 2001 IEEE International Conference on Data Mining
Managing power and performance for System-on-Chip designs using Voltage Islands
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
HPCA '02 Proceedings of the 8th International Symposium on High-Performance Computer Architecture
Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
ACM Transactions on Embedded Computing Systems (TECS)
Architecting voltage islands in core-based system-on-a-chip designs
Proceedings of the 2004 international symposium on Low power electronics and design
Architecting voltage islands in core-based system-on-a-chip designs
Proceedings of the 2004 international symposium on Low power electronics and design
Efficient search space exploration for HW-SW partitioning
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Hardware/software partitioning of software binaries: a case study of H.264 decode
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
GALDS: a complete framework for designing multiclock ASICs and socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A computing origami: folding streams in FPGAs
Proceedings of the 46th Annual Design Automation Conference
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Modern systems-on-a-chip platforms support multiple clock domains, in which different sub-circuits are driven by different clock signals. Although the frequency of each domain can be customized, the number of unique clock frequencies on a platform is typically limited. We define the clock-frequency assignment problem to be the assignment of frequencies to processing modules, each with an ideal maximum frequency, such that the sum of module processing times is minimized, subject to a limit on the number of unique frequencies. We develop a novel polynomial-time optimal algorithm to solve the problem, based on dynamic programming. We apply the algorithm to the particular context of post-improvement of accelerator-based hardware/software partitioning, and demonstrate 1.5x-4x additional speedups using just three clock domains.