Hardware assisted watermarking for multimedia
Computers and Electrical Engineering
GALDS: a complete framework for designing multiclock ASICs and socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Variability-aware architecture level optimization techniques for robust nanoscale chip design
Computers and Electrical Engineering
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In this paper, we propose a VLSI architecture and provide prototype implementation of a chip that can insert both invisible and visible watermarks in DCT domain. To our knowledge, this is the firstever low power watermarking chip having such watermarking functionalities. Various techniques, such as multiple voltages, multiple frequency, and clock gating are incorporated to reduce power consumption of the chip. The proposed architecture has a three stage pipeline structure and also uses parallelism to improve the overall performance. A prototype chip is designed and verified using various Cadence and Synopsys tools using TSMC 0.25µ technology. It runs at a dual frequency of 280MHz and 70MHz and at a dual voltage of 2.5V and 1.5V and contains 1.4M transistors. The average power consumption of the chip is estimated to be 0.3mW, which is five times less than its single supply voltage and single frequency operation.