On the Transistor Sizing Problem

  • Authors:

  • Abhijit Das

  • Affiliations:

  • -

  • Venue:
  • VLSID '00 Proceedings of the 13th International Conference on VLSI Design
  • Year:
  • 2000

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Abstract

This paper introduces a new transistor sizing technique for timing optimization in a transistor level netlist. Starting from an initial solution, the widths of the transistors in the netlist are tuned iteratively to meet the specified timing constraints. Efficient heuristics to significantly improve the run time performance are outlined. The improvement of timing and area performance are demonstrated with several real circuits.