Can Redundancy and Masking Improve the Performance of Synchronizers?
IEEE Transactions on Computers
Investigation into micropipeline latch design styles
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Digital systems engineering
On Limitations and Extensions of STG Model for Designing Asynchronous Control Circuits
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Single-rail handshake circuits
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
The Anomalous Behavior of Flip-Flops in Synchronizer Circuits
IEEE Transactions on Computers
Anomalous Behavior of Synchronizer and Arbiter Circuits
IEEE Transactions on Computers
Anomalous Response Times of Input Synchronizers
IEEE Transactions on Computers
Robust interfaces for mixed-timing systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System level power and performance modeling of GALS point-to-point communication interfaces
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Toward a multiple clock/voltage island design style for power-aware processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Metastability in Asynchronous Wait-Free Protocols
IEEE Transactions on Computers
An architecture and a wrapper synthesis approach for multi-clock latency-insensitive systems
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
A predictive synchronizer for periodic clock domains
Formal Methods in System Design
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Computing synchronizer failure probabilities
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 44th annual Design Automation Conference
Integration, the VLSI Journal
The choice uncertainty principle
Communications of the ACM
A Survey and Taxonomy of GALS Design Styles
IEEE Design & Test
Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook
IEEE Design & Test
Performance Evaluation of Elastic GALS Interfaces and Network Fabric
Electronic Notes in Theoretical Computer Science (ENTCS)
Parallel vs. serial on-chip communication
Proceedings of the 2008 international workshop on System level interconnect prediction
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Two-phase synchronization with sub-cycle latency
Integration, the VLSI Journal
Multi-Clock Latency-Insensitive Architecture and Wrapper Synthesis
Electronic Notes in Theoretical Computer Science (ENTCS)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 7th ACM international conference on Computing frontiers
Analysis and optimization of pausible clocking based GALS design
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Fault Modeling and Analysis for Resistive Bridging Defects in a Synchronizer
Journal of Electronic Testing: Theory and Applications
Early set to zero micro-pipeline
Proceedings of the 11th International Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing on International Conference on Computer Systems and Technologies
A general method to make multi-clock system deterministic
Proceedings of the Conference on Design, Automation and Test in Europe
Modeling and evaluation of ring-based interconnects for Network-on-Chip
Journal of Systems Architecture: the EUROMICRO Journal
A hardwired NoC infrastructure for embedded systems on FPGAs
Microprocessors & Microsystems
GALDS: a complete framework for designing multiclock ASICs and socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Synchronous design flow for globally asynchronous locally synchronous systems
ICC'06 Proceedings of the 10th WSEAS international conference on Circuits
Truncation error analysis of MTBF computation for multi-latch synchronizers
Microelectronics Journal
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
VLSI implementation of a distributed algorithm for fault-tolerant clock generation
Journal of Electrical and Computer Engineering - Special issue on Clock/Frequency Generation Circuits and Systems
Proceedings of the Conference on Design, Automation and Test in Europe
Test generation for clock-domain crossing faults in integrated circuits
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.02 |
Transferring data between mutually asynchronous clock domains requires safe synchronization. However, the exact nature of synchronization sometimes eludes designers, and as a result synchronization circuits get "optimized" to the point where they do no longer operate correctly. This paper reviews a number of such cases, analyzes the causes of the errors, and offers a correct synchronizer circuit for each case. A correct two-flop synchronizer is presented. After discussing cases that avoid synchronization, the following synchronizers are reviewed: one flop, sneaky path, greedy path, wrong protocol, global reset, async clear, DFT leakage, pulse, slow-to-fast, metastability blocker, parallel and shared flop synchronizers.