Anomalous Behavior of Synchronizer and Arbiter Circuits
IEEE Transactions on Computers
Reliable High-Speed Arbitration and Synchronization
IEEE Transactions on Computers
Metastability evaluation method by propagation delay distribution measurement
ATS '95 Proceedings of the 4th Asian Test Symposium
Fourteen Ways to Fool Your Synchronizer
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Comments on "The Anomalous Behavior of Flip-Flops in Synchronizer Circuits"
IEEE Transactions on Computers
IEEE Transactions on Computers
Synchronization and Matching in Redundant Systems
IEEE Transactions on Computers
Equivalence of the Arbiter, the Synchronizer, the Latch, and the Inertial Delay
IEEE Transactions on Computers
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IEEE Transactions on Computers
Measured Flip-Flop Responses to Marginal Triggering
IEEE Transactions on Computers
General theory of metastable operation
IEEE Transactions on Computers
IEEE Transactions on Computers
Constructive Boolean circuits and the exactness of timed ternary simulation
Formal Methods in System Design
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This paper deals with an anomalous behavior of input synchronizers which results in the occurrence of random errors in asynchronously interfaced synchronous digital systems. The errors are caused by the undefined response time of a flip-flop as it recovers from its metastable state. To obtain their frequency, the timing diagram of the flip-flops has been analyzed and the probability distribution of the anomalous response times has been measured. As an example, maximum response time of SN74S74 is estimated on the basis of a set of statistical measurements. The measurement technique presented may be used for any type of input synchronizer. Two well-known methods of reducing failure probability for SN74S74 are evaluated. Two fundamental solutions of the metastable-state problem in the clocked systems are described.